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| Features * Comprehensive Library of Standard Logic Cells * ATC35 I/O Cells Designed to Operate with VDD = 3.3V 0.3V as Main Target Operating Conditions IO35 Pad Library Provides Interface to 5V Environment Oscillators and Phase Locked Loops for Stable Clock Sources Memory Cells Compiled to the Precise Requirements of the Design Compatible with Atmel's Extensive Range of Microcontroller, DSP, Standard Interface and Application Specific Cells * High-Performance Analog Cells can be Developed on Request * * * * Cell-based ASIC ATC35 Summary Description The Atmel ATC35 (AT56K) process is a proprietary 0.35 micron three-layer-metal CMOS process intended for use with a supply voltage of 3.3V 0.3V. The following table shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol VDD3 VDD5 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Industrial Conditions Core and Standard I/Os 5V Interface I/Os Min 3.0 4.5 0 0 -55 Typ 3.3 5.0 Max 3.6 5.5 VDD VDD +85 Unit V V V V C The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: * MIN conditions: TJ = -55C VDD (cell) = 3.60V Process = fast (industrial best case) * TYP conditions: TJ = +25C VDD (cell) = 3.30V Process = typ (industrial typical case) * MAX conditions: TJ = +100C VDD (cell) = 3.00V Process = slow (industrial worst case) Delays to tristate are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Rev. 1063CS-CBIC-01/03 1 Standard Cell Library SClib The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic and storage cells. The SClib library includes cells which belong to the following categories: * * * * * * Buffers and Gates Multiplexers Flip-flops Scan Flip-flops Latches Adders and Subtractors Decoding the Cell Name The table below shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available. Table 2. Cell Codes Code AD AN AOI AON AOR BH BUFF BUFT CLK2 DE DF INV0 INVB INVT JK LA Description Adder AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Bus Holder Non-Inverting Buffer Non-Inverting 3-State Buffer Clock Buffer D-Enabled Flip-Flop D Flip-Flop Inverter Balanced Inverter Inverting 3-State Buffer JK Flip-Flop D Latch Code LASR MI MFF MX ND NR OAI OAN OR ORA SD SE SRLAB SU XN XR Description Set/Reset Latch Inverting Multiplexer Multiplexed flip-flop with Feedback Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-Flop Multiplexed Scan Enable D Flip-Flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate 2 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary Cell Matrices The following three tables provide a quick reference to the storage elements in the SClib library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Macro Name JKBRBx Set Clear 1x Drive 2x Drive * * * * Table 4. D Flip-flops Macro Name DFBRBx DFCRBx DFCRQx DFCRNx DFNRBx DFNRQx DFPRBx DEPRQx DECRQx Set Clear Enabled D Input 1x Drive 2x Drive Single Output * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Table 5. Scan Flip-flops Macro Name DENRQx MFFNRBx SDBRBx SDCRBx SDCRNx SDCRQx SDNRBx SDNRNx SDNRQx SDPRBx SECRQx SENRQx SEPRQx Set Clear 1x Drive 2x Drive Single Output * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 3 1063CS-CBIC-01/03 Input/Output Pad Cell Libraries IOlib and IO35lib Voltage Levels The Atmel Input/Output Cell Library, IOlib, contains a comprehensive list of input, output, bidirectional and tristate cells. The ATC35 (AT56K) (3.3V) cell library includes a special set of I/O cells, IO35lib, for interfacing with external 5V devices. The IOlib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 3.0V to 3.6V. The library is compatible with the SClib 3-volt standard cells library. Designers are strongly encouraged to provide three kinds of power pairs for the IOlib library. These are "AC", "DC" and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance. Table 6. VSS Power Pad Combinations Core Vssi Switching I/O VssAC Quiet I/O VssDC Library Cell Name PV0I Power and Ground Pads Signal Name VSS VSS VSS VSS VSS VSS * * * * * * * * * * PV0A PV0D PV0E PV0B PV0F Table 7. VDD Power Pad Combinations Core Vddi Switching I/O VddAC Quiet I/O VddDC Library Cell Name PVDI Signal Name VDD VDD VDD VDD VDD VDD * * * * * * * * * * PVDA PVDD PVDE PVDB PVDF 4 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary Cell Matrices Table 8. CMOS Pads CMOS Cell Name PC3B01 PC3B02 PC3B03 PC3B04 PC3B05 PC3O01 PC3O02 PC3O03 PC3O04 PC3O05 PC3T01 PC3T02 PC3T03 PC3T04 PC3T05 3-State I/O Output Only 3-State Output Only Drive Strength 1x 2x 3x 4x 5x Pad Sites Used 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 * * * * * * * * * * * * * * * 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x Table 9. TTL Pads TTL Cell Name PT3B01 PT3B02 PT3B03 PT3O01 PT3O02 PT3O03 PT3T01 PT3T02 PT3T03 3-State I/O Output Only 3-State Output Only Drive Strength 2 mA 4 mA 8 mA Pad Sites Used 1 1 1 1 1 1 1 1 1 * * * * * * * * * 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA Table 10. CMOS/TTL Input Only Pad CMOS Cell Name PC3D01 PC3D11 PC3D21 PC3D31 Input Levels CMOS CMOS CMOS CMOS Schmitt Input Level Shifter Non-Inverting Inverting Pad Sites Used 1 * * * * * * 1 1 1 Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. 5 1063CS-CBIC-01/03 Table 11. Core-driven Clock Buffer Pads Cell Name PC3C01 PC3C02 PC3C03 PC3C04 Drive Strength 1x 2x 3x 4x Non-Inverting vddDC Pad Pad Sites Used 1 1 1 1 * * * * * * * * IO35lib Low Slew Rate Cells All IO35lib cells are slew rate controlled. Advantage has been taken of the 3.3V to 5V level shifter (which is slow by construction) to reduce the slew rate without reducing speed. Table 12. IO35lib Pads 5V Interface Pad Name mc5b0x mc5d00 mc5o0x mc5t0x 3-State I/O Output Only 3-State Output Only Input Only Drive Strength 2 mA, 4 mA, 8 mA, 16 mA Pad Sites Used 1 1 2 mA, 4 mA, 8 mA, 16 mA 1 1 * * * * 2 mA, 4 mA, 8 mA, 16 mA Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. Table 13. IO35lib Power Pads Power Bus Connections Cell Name mv0e mv0i mv3i mv5e mc45frell, mc45freur mc45frelr, mc45freul mc45fr0ll, mc45fr0ur vssi mixvss vddi mixvdd Pad Sites Used 1 1 * * * * * * * * * 1 1 4 4 4 6 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary Oscillator Cell Library Osclib Crystal Oscillators and Power on Reset The Atmel CBIC oscillator library provides stable clock sources. This library makes the following cells available: The Atmel two-pad oscillators are designed with the Pierce three-point oscillator structure. For operation with most standard crystals, no external capacitors are needed. It may be necessary to add external capacitors on xin and xout to ground in special cases. Clock output is low at off state (onosc = 0). The oscillators provide a test mode (test = 1 and onosc = 1), clock = not (xin). The Atmel Power-on-reset cell is dedicated to reset the internal circuit at power up and when the battery falls low. Table 14 gives available oscillator and POR cells. Table 14. Oscillator and POR Cells Cell Name osc33k osc16m osc27m GNDYPOR Description Low-power, optimized for 32.786 kHz crystal 16 MHz crystal oscillator 27 MHz crystal oscillator Ground pad for periphery with power on reset. Static and dynamic reset with internal hysteresis. Phase Locked Loops The Atmel PLLs are systems designed for synchronizing an internal chip clock with an input reference clock or multiplicating an input reference clock. Table 15 gives available phase locked loop cells. Table 15. Phase Locked Loop Cells Cell Name pll020m1 pll080m1 pll220m1 Description 5 - 20 MHz single-pad phase locked loop 20 - 80 MHz single-pad phase locked loop 80 - 220 MHz single-pad phase locked loop Basic Analog Cell Library AnaLib The Atmel CBIC Analog Library makes the following parts available: * Multiplexer modules - - * * Multiplexers to minimize cross-talk (for use with high-impedance nodes). Multiplexers to minimize ON resistance. Analog input and output cells Analog power and ground cells General-purpose Analog Library GPlib The General-purpose Analog Cell Library is composed of cells performing various analog functions. Currently available are regulators, power management cells, op amps, comparators, low-speed ADCs and DACs. 7 1063CS-CBIC-01/03 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the functions ARAM (Advanced Random Access Memory), Dual-Port RAM, FIFO (First In First Out), ROM, and LROM (Large ROM) according to the user's precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, layout generation, place and route, and verification are created automatically. The Built-In Self-Test (BIST) option, in terms of a netlist of standard cells surrounding the megacell, is supported for all megacells except the LROM (in this release). FIFO and FIFO with BIST are available through the Cgenerate as netlists of standard cells surrounding a Dual-Port RAM Megacell. Compiled ARAM Megacells The Atmel ARAM compiler builds Clocked Embedded Self-timed Static RAMs from a set of input parameters, for example, the number of words and the word width. The Atmel ARAM generator is capable of creating many different sizes of RAM. In addition, for any given size, many configurations are possible. The differences in these configurations can be found in the aspect ratio and in performances. The range of permitted ARAM megacell configurations is as follows: Max number of bits Number of words Number of rows 256K bits 64, .. 32768 32, .. 256 2, 4, 8 1, 2, 4, 8, 16 1, .. 128 increment of 1 4, .. 32 if no. of columns per bit = 2 2, .. 16 if no. of columns per bit = 4 1, .. 8 if no. of columns per bit = 8 multiples of 32 multiples of 16 Number of columns per bit (words per row per block) Number of blocks Number of bits in a word: if no. of blocks = 1 if no. of blocks > 1 The following table lists all ARAM inputs and outputs and their pin capacitances. Pin Name ME WE_ ADD DI 8 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary The following tables show the range of performances for particular ARAM configurations without BIST and without CLoad. Access time (tACC) and cycle time (tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. Word Size = 8 Word Depth Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 256 0.264 0.609 5.53 5.53 0.20 512 0.430 0.634 5.78 5.78 0.33 1K 0.430 1.078 6.52 6.74 0.43 2K 1.514 0.647 7.08 7.08 0.29 4K 1.514 1.091 7.81 8.26 0.37 8K 2.844 1.097 8.62 9.10 0.64 16K 5.607 1.097 9.36 9.74 0.84 32K 5.607 1.984 10.83 12.68 0.96 Word Size = 16 Word Depth Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 128 0.430 0.387 5.33 5.33 0.26 256 0.430 0.609 5.70 5.70 0.39 512 0.765 0.634 5.95 5.95 0.66 1K 0.765 1.078 6.69 6.94 0.85 2K 2.852 0.647 8.38 8.38 0.63 4K 2.852 1.091 9.11 9.54 0.79 8K 5.607 1.091 9.86 10.18 1.08 16K 5.607 1.978 11.33 13.12 1.22 Compiled Dual-Port RAM The Atmel Dual-Port RAM is a read/write memory that allows access to and from its memory cells by two independent ports (identified as Port A and Port B). There are no Megacells constraints on the timing of the ports relative to each other except in the case of address contention. Although the ports are constructed from the same circuitry, the possible I/O configurations are different: * * Port A may be selected with read/write or read-only capability Port B can have read/write or write-only capability The two ports may have different wordlengths, provided that the ratio is an integral power of 2 (1, 2, 4, 8, 16, 32 or 64). The product (wordlength x address space) must be the same for the two ports. The memory cell corresponds to a standard full CMOS six-transistor cell with the benefit of extremely low standby power dissipation. (There are actually eight or ten transistors per cell, according to the configuration of the port A). Dual-Port RAM operates in single-edge clock controlled mode during read operations, and a double-edge controlled mode during write operations. Addresses are clocked internally on the rising edge of the clock signal (ME). Any change of address without rising edge of ME is not considered. In read mode, the rising clock edge triggers a data read without any significant constraint on the length of the ME pulse. In write mode, data applied to the inputs is latched on the falling edge of ME or the rising edge of WE_, whichever comes earlier, and is then written in memory. 9 1063CS-CBIC-01/03 The range of permitted Dual-Port RAM Megacell configurations is as follows: Number of rows: Number of cols: 4, ...128 2, ...128 Number of words: 8, ...16384 Bits per word: Total size: 1, ...64 8, ...16384 Port A configuration: read/write, read-only Port B configuration: read/write, write-only The following table lists all DPR inputs and outputs and their pin capacitances. Pin names are suffixed with the port nature A or B: Pin Name ME WE_ ADD DI The following tables show the range of performances for particular Dual Port RAM configurations, without BIST and without output load. Access time (tACC) and cycle time (tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. All examples have the same configuration for both port A and port B, with Read/Write capability. Word Size = 8 Word Depth Rows x Columns Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 128 32 x 32 0.416 0.384 3.30 5.89 0.31 256 64 x 32 0.422 0.615 3.68 6.41 0.46 512 64 x 64 0.685 0.620 4.06 6.92 0.81 1K 128 x 64 0.702 1.082 4.81 7.43 1.36 2K 128 x 128 1.228 1.087 5.55 7.95 2.59 Word Size = 16 Word Depth Rows x Columns Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC)(nsec) Dynamic Power (mW/MHz) 64 32 x 32 0.416 0.387 3.27 5.38 0.32 128 64 x 32 0.422 0.618 3.65 6.01 0.46 256 64 x 64 0.685 0.614 3.98 6.41 0.82 512 128 x 64 0.702 1.076 4.72 6.92 1.37 1K 128 x 128 1.228 1.081 5.36 7.43 2.6 10 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary Compiled FIFO Megacells A compiled FIFO (first-in first-out data flow) megacell is implemented as a soft macro built around a Dual-Port RAM. The compiled FIFO is a buffer memory that allows access to its memory cells by two independent ports. The read port is referred to as port A, the write port is labelled port B. Both ports are controlled by independent clock signals and contain address counters which are incremented during every clock cycle. The FIFO block makes use of a compiled Dual-Port RAM with the configuration port A read-only and port B write-only. Number of rows: Bits per word: Total size: 2, ...128 in increments of 2 1, ...64 8, ...16384 Number of words: 8, 16, 32, ...16384 The word lengths of both ports may be different, but their ratio must be one of (1, 2, 4, 8, 16, 32 or 64). The following is a list of pins which will be found on the symbol of a module: * CKOUT is the clock input for port A (read port). * * * * * * * CKIN is the clock input for port B (write port). DIN<0:i-1> Data input lines. DOUT<0:i-1> Data output lines. RESETZ The clear signal. EMPTY The empty flag. FULL The full flag. Supply (VDD) and ground (GND). The following table shows the estimated range of performance for particular FIFO configurations, without BIST, and without output load. Access time (tACC) and cycle time (tCYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. All examples have the same configuration for both port A and port B, with Read/Write capability. There is no additional flag. Word Size Word Depth Rows x Columns Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 4 16 8x8 0.235 0.169 2.72 4.55 0.10 8 32 16 x 16 0.307 0.227 2.91 4.86 0.15 16 64 32 x 32 0.455 0.342 3.27 5.38 0.31 32 128 64 x 64 0.724 0.573 3.97 5.89 0.80 64 256 128 x 128 1.267 1.035 5.37 7.56 2.58 11 1063CS-CBIC-01/03 Compiled ROM Megacells Compiled memories are diffusion-programmed ROMs with a synchronous access protocol. The generated ROM Megacell is a single edge control ROM. Rising edge of the memory enable signal (ME) latches the addresses and starts the read operation. The internal idle state of the memory plane is the precharge state. The next clock cycle can start with the next ME rising edge, once the precharge is complete. The generator takes care of complementing the required address space to the nearest physical size possible in case of number of words being not equal to an integral power of two. The range of permitted ROM configurations is as follows : Number of words: Bits per words: Total size: Number of Columns: Number of Rows: 9...16384 1...128 9...131072 4...512 4...256 (128K) Number of Address Bits: 4...14 The memory plane is organized in multiples of 4 rows, and multiples of 4, 8, 16, 32 or 64 columns. The following table lists all ROM inputs and outputs and their pin capacitances: Pin Name ME OE ADD DO The following tables show the range of performances for particular ROM configurations. Access time (tACC) and cycle time (t CYC) refer to Max industrial conditions, whereas Dynamic Power dissipation refers to typical conditions. Word Size = 8 Word Depth Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 16 0.234 0.158 3.62 5.88 0.20 32 0.234 0.164 3.66 5.91 0.21 64 0.234 0.177 3.73 5.99 0.21 128 0.234 0.203 3.89 6.14 0.22 256 0.297 0.203 3.93 6.18 0.24 512 0.297 0.254 4.23 6.48 0.28 1K 0.423 0.254 3.66 6.56 0.35 Word Size = 16 Word Depth Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 16 0.297 0.158 3.66 5.95 0.34 32 0.297 0.164 3.70 5.99 0.35 64 0.297 0.177 3.77 6.06 0.35 128 0.297 0.203 3.93 6.21 0.37 256 0.297 0.254 4.23 6.51 0.41 512 0.423 0.254 4.31 6.59 0.48 1K 0.423 0.357 4.92 7.19 0.63 12 ATC35 Summary 1063CS-CBIC-01/03 ATC35 Summary Compiled LROM Megacells The LROM (Large ROM) compiler allows the system designer to acheive high-density and low-power applications. Multi-block megacells with total capacity up to 4M-bits can be generated by the LROM compiler. Compiled memories are diffusion-programmed ROMs with a synchronous access protocol, as is for the ROM. The compiler expects a programming file: lrom Total size: Bits per word: 64K...4M 8, 16 or 32 Number of words: 2K...512K Number of address bits:11...19 The memory is organized in multiple blocks of 64K bits each. Number of blocks: Number of rows per block: 1...32 256 Number of columns per block:256 I/O pins in compiled megacells are the following: me input: Memory Enable. add inputs: Address. do outputs: buffered output data. vdd and gnd: power and ground supplies. The following table shows the performances for some LROM configurations. Access time (tACC), cycle time (tCYC) and Dynamic Power dissipation refer to Max industrial conditions. Word Size = 16 Word Depth Width (mm) Height (mm) Access Time (tACC) (nsec) Cycle Time (tCYC) (nsec) Dynamic Power (mW/MHz) 16K 0.979 0.858 11.37 14.15 0.26 32K 3.570 0.539 11.84 14.40 0.56 64K 1.863 1.716 12.53 15.30 0.75 128K 1.863 3.078 15.19 19.14 0.90 13 1063CS-CBIC-01/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 1063CS-CBIC-01/03 0M |
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